IPSOAR 提供了業(yè)界極具競爭力的memory compiler產(chǎn)品,通過全手工定制打造Memory compiler產(chǎn)品,滿足客戶在面積、速度、功耗上的極致需求,幫助客戶提高產(chǎn)品競爭力。
IPSOAR memory compiler通過獨(dú)有的低功耗設(shè)計(jì)方案,靜態(tài)漏電流同比業(yè)界降低30~50%;同時(shí)支持三種低功耗模式(Nap,Retention,Power down),滿足客戶對不同低功耗模式下的需求。
IPSOAR memory compilers 提供了業(yè)界領(lǐng)先的EDA 模型,包括datasheet, verilog behavior mode, liberty model, P&R model, DFT model等。
能夠提供工藝節(jié)點(diǎn)從0.18um 到 7nm 先進(jìn)工藝平臺(tái)的產(chǎn)品。
Highlights:
IPSOAR memory compiler通過獨(dú)有的低功耗設(shè)計(jì)方案,靜態(tài)漏電流同比業(yè)界降低30~50%;同時(shí)支持三種低功耗模式(Nap,Retention,Power down),滿足客戶對不同低功耗模式下的需求。
IPSOAR memory compilers 提供了業(yè)界領(lǐng)先的EDA 模型,包括datasheet, verilog behavior mode, liberty model, P&R model, DFT model等。
能夠提供工藝節(jié)點(diǎn)從0.18um 到 7nm 先進(jìn)工藝平臺(tái)的產(chǎn)品。
Highlights:
● Process variation tolerance design technique to improve yield
● Reduce memory hard failure to improve yield by considering critical DFM rule
● Auto leakage control technique to reduce standby current
● Fully customized and optimized layout to get minimum area
● Ultra faster memory compiler engine “Meminder” to generate memory instance rapidly
Deliverables:
可視化圖形界面:
Deliverables:
● Verilog timing/simulation model
● VHDL timing/simulation model
● Spice-level netlist for LVS
● GDSII layout database
● Physical bitmap support
● Timing/Power/Noise liberty model
● P&R model
● Memory BIST model
可視化圖形界面:
Products | Memory Type |
---|---|
Memory Compiler | High Density Single Port SRAM |
High Density One Port Register File | |
High Speed Single Port SRAM | |
High Speed One Port Register File | |
Two Port Register File | |
Two Port SRAM | |
Dual Port SRAM | |
Ultra high density two port register file (one clock) | |
Ultra high density two port SRAM (one clock) | |
Via ROM | |
TCAM | |
Special Multi-Port SRAM |